1. Field of the Invention
The present invention relates to semiconductor memories, and more particularly pertains to a semiconductor memory employing a direct sensing scheme.
2. Discussion of the Prior Art
The evolution of sub-micron CMOS technology has resulted in significant improvement in microprocessor speeds. Quadrupling roughly every three years, microprocessor speeds have now even exceeded 1 Ghz. Along with these advances in microprocessor technology have come more advanced software and multimedia applications, requiring larger memories for the application thereof. Accordingly, there is an increasing demand for memories with higher density and performance.
Historically, direct sense circuitry has been added to the conventional cross-coupled CMOS pair sense amplifier in memory arrays to improve sensing speed. This is accomplished in two ways: firstly, the signal developed on the bitline can be transferred to the data line before a significant separation between the bitlines has been performed by the cross-coupled pair; and secondly, because the bitline is terminated into the gate of a transistor with its drain connected to the data line, the bitline and data line are de-coupled during the read operation.
FIG. 1 is a circuit schematic for a direct sense amplifier architecture as described by the prior art. The conventional cross-coupled CMOS pair sense amplifier is comprised of devices N7, N8, P1, and P2. The devices N9, N10, and N11 make up the bitline pre-charge circuitry.
The four transistors N1, N2, N3, and N4 form the direct sense read circuitry. When the signal RE goes high, data on the bitlines (BLt and BLc) is transferred to differential data lines MDQt and MDQC. The devices N5 and N6 form a write mode switch to transfer data from the differential data lines MDQt and MDQc to the bitlines BLt and BLc.
Referring to FIG. 2, the operation of the direct sense amplifier proceeds as follows utilizing a Vdd/2 pre-charge scheme. It is assumed that a storage cell stores a physical xe2x80x9c0xe2x80x9d data. When WL is activated, the physical xe2x80x9c0xe2x80x9d charge in the storage cell equalizes with charge on the bitline and BLc develops a small negative potential difference with respect to BLt. When the signal RE is asserted, a small differential signal (opposite in polarity with respect to the bitline signal) starts to develop on the data lines MDQt/c which were originally pre-charged to a high potential. As the PCS and NCS nodes are asserted, the cross-coupled pair begins to separate the bitlines, eventually realizing a full potential separation defined by the supply voltages of PCS and NCS. As the bitlines separate, the transistor N2 begins to turn on as BLt approaches the maximum value of PCS and pulls the data line MDQt to the ground potential. Conversely, transistor N1 turns off as BLc approaches the minimum value of NCS and MDQc remains at a high potential with respect to MDQt. A secondary sensing circuit (not shown) located at the opposite end of the data lines extracts the signal from the data lines. For a write mode, a signal WE goes high, and this couples the data lines MDQt and MDQ to the bitlines BLt and BLc. This functions to overwrite a data pattern on the bitlines BLt and BLc by forcing the bitline voltage by the MDQt and MDQc to the corresponding data pattern.
The advantage of this direct sensing scheme can be realized by observing that the signal is transferred to the data lines as it develops on the bitlines. Direct sense amplification accelerates the signal transfer as compared to a conventional cross-coupled sense amplifier operation as the later requires that the separation on the bitlines be enough that coupling to the heavily capacitive data lines through pass gates does not destroy the signal on the bitlines. Further, for this reason, the timing of the RE signal for the direct sense amplifier operation in comparison to the CSL (column select line) of the conventional approach is much less critical. This results in a high speed access time.
The existing direct sensing scheme does, however, have three disadvantages. (1) Additional direct sensing devices increase the silicon area. (2) A cycle time is not improved, because it is determined by a signal write back operation, which consists of a signal development on the bitlines, CMOS cross-coupled sensing operation, and writing back the amplified signal on the bitline to the capacitor of the cell. (3) The intra and inter bitline coupling noise in a CMOS cross-coupled sensing operation remains, reducing a signal margin.
The present invention:
improves memory cycle time by using a single bitline direct sensing architecture.
reduces memory silicon area by using a single bitline direct sensing architecture.
improves memory sensing margin by shielding every other bitline by using a single bitline direct sensing architecture.
reduces memory cycle time by allowing a small bitline swing in a read mode with a single bitline direct sensing architecture.
reduces memory cycle time by naturally allowing a precondition for a delayed write in a destructive read architecture.
provides a method to sense a cell voltage without having a CMOS cross coupled-sense amplifier.
improves a bandwidth of a memory cell by transferring all of the data bits activated by the wordline simultaneously.
provides a method to transfer all of the data bits sensed into the data lines simultaneously without having a wiring problem.
provides a method to arrange the read and write data lines over the array to allow all of the data bits accessed in a first memory array to be read, while allowing all the data bits accessed in a second memory array to be written without having a wiring problem.
senses a data bit with a simple inverter.
improves memory sensing margin by shielding every other bitline by independently controlling the bitline precharge circuitry and multiplexer with a CMOS Cross-coupled sense amplifier.
In a first aspect of the invention, there is provided a single bitline sensing architecture for dynamic random access memories. The single bitline sensing architecture employs a NMOS device, which couples to the bitline (gate), the single global data line (drain), and a switching device (source). Alternatively, the single bitline sensing architecture employs a NMOS device, which couples to the bitline (gate), a switching device (drain) to couple the single global data line, and the ground potential node (source). The NMOS conductance is changed when the data bit is transferred to the bitline in a signal development phase. By enabling the switching device, the NMOS conductance difference for a 0 and 1 data bit is globally detected by monitoring a voltage on the data line. This results in a digital sensing scheme with a simple inverter coupling to the single global data line. Because of this simplicity, all of the data bits activated by the wordline can be transferred to the corresponding single global data lines simultaneously without having a global wiring problem. This results in an ultimate bandwidth. Optionally, the current may be monitored on the single global data line with a current sensing scheme.
In another aspect of the invention, there is a provided a single bitline sensing architecture for short cycle time dynamic random access memories. By employing a destructive read architecture (A Destructive Read Architecture for Dynamic Random Access Memories, FIS92000411, Kirihata et al.), no CMOS cross-cross-coupled sense amplifiers are required, since a write mode operation is scheduled as a delayed write described in the destructive read architecture. This results in a small silicon area while enabling a small bitline voltage swing sensing scheme for further improving cycle time. The VDD precharged bitline without having a CMOS cross-coupled sense amplifiers naturally generates a precondition state (Method and Apparatus for Reducing Write Operation Time in Dynamic Random Access Memories, FIS920000410US1, Kirihata et. Al.) for a future delayed write back, further improving a cycle time in a write mode.
In yet another aspect of the invention, there is provided a single bitline sensing architecture for shielding bitline in a sensing operation. The single bitline sensing architecture allows every other bitlines to be used for shielding the other every other bitlines in a sensing operation, increasing memory sensing margin.